1. Field
The following description relates to an instruction set architecture (ISA) for a computer architecture, and more particularly, to instruction compression for an instruction-level parallelism architecture such as a very long instruction word (VLIW) computer architecture.
2. Description of the Related Art
A very long instruction word (VLIW) computer architecture refers to a central processing unit (CPU) architecture designed for processing instructions according to an instruction-level parallelism (ILP). A VLIW computer includes a plurality of functional units (FUs) for executing multiple instructions simultaneously. Instructions input to the VLIW computer may be divided into instruction groups such that the number of instructions corresponds to the number of FUs. The term instruction group is also referred to as an instruction bundle in which the instructions are executed by the multiple FUs concurrently. Because instructions belonging to one instruction bundle may be allocated to the respective FUs and processed concurrently, the VLIW computer can reduce time for processing the total number of instructions.
The maximum number of instructions that may be processed simultaneously by an ILP computer such as a VLIW computer is theoretically the same as the number of FUs. However, due to the dependency between the instructions, the number of instructions that may be executed simultaneously may be smaller than the number of the FUs. For example, a situation frequently occurs where some or all of the FUs cannot process a certain instruction because an operation result according to a previous instruction is needed to execute the certain instruction and is not yet obtained. Accordingly, the VLIW computer allocates a no-operation (NOP) instruction to a FU such that the FU does not process instructions at that time.
Because of the additional NOP instructions, the total number of instructions in the VLIW computer is increased, thereby causing performance degradation. Because the total number of instructions is increased, a memory of a large capacity is usually required. In addition, the probability of cache miss occurring due to the large capacity of the memory is increased, which may lead to reduction of the overall system speed. Furthermore, the large number of instructions may also incur instruction fetch overhead.
To prevent the performance degradation of the VLIW computer, various studies on instruction compression for compressing and storing instructions have been performed. For example, the instruction compression methods may involve a stop-bit or a parallel-bit (p-bit) that is allocated to an instruction to inform of the stopping of a valid instruction in an instruction group or a to a group header that is assigned to the instruction group that is used to indicate the size of a group and a location of a NOP instruction. Also, a method has been suggested to compress instructions by inserting an index code that indicates the number of subsequent NOP instructions. The index code may be inserted into a valid instruction in the same instruction group or into each valid instruction for indicating the order of executing valid instructions in the same instruction group.